This invention relates to a dynamic random access memory (DRAM) of semiconductor device and particularly to a data transmission circuit with a high data access time.
A general tendency in semiconductor device field is toward higher density of the semiconductor device as well as higher operational speed thereof. However, if the semiconductor device meets the demand for the higher density, its operational speed is lowered; contrastingly if the semiconductor device is made so as to increase the operation speed, the density of the semiconductor device is lowered. Therefore, in order to meet both demands for the higher density and higher operation speed of the semiconductor device, the structure of the data transmission circuit and the elements used therefor must be carefully considered and selected.
Referring to FIGS. 1 and 2, typical conventional data transmission circuits are described, wherein the circuit of FIG. 1 shows a compact structure having common input/output lines 5, 6 through which the data are transmitted. The data transmission circuit of FIG. 1 is a detailed view of a specific part of the semiconductor memory cell array. In structure, the conventional data transmission circuit is comprised of bit lines 1 and 2 coupled to a memory cell (not shown), the common input/output lines 5 and 6, input/output transistors 3 and 4 for connecting the bit lines with the common input/output lines, and a sense amplifier 7 operating in response to control signals .phi..sub.S, .phi..sub.SD. The input/output transistors 3 and 4 operate in response to a column selection line (CSL) signal. The sense amplifier 7 is a generally known type and thus, a concrete view thereof is not described.
As can be understood from FIG. 1, such compact scheme is favorable to a higher density of the semiconductor device. However, the common input/output line's loading is relatively much smaller than the bit line's loading, so that the weak signals from the bit lines 1, 2 can be hardly delivered into the common input/output lines. Therefore, the sense amplifier 7 is used for amplifying the weak signals and the time taken for amplifying the signals is called the sensing time. The real sensing time of this conventional circuit is about 5-10 ns which quite long and the sensing time is greatly affects the data access time. Accordingly, if the sensing time is longer, the data access time is longer, too. In conclusion, the circuit of FIG. 1 is favorable to a higher density of the semiconductor device, however the fast data access time cannot be realized.
In FIG. 2, another conventional data transmission circuit for solving the above problem is proposed. This circuit employs the direct sensing method disclosed in pages 1102-1109, IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990. In structure, the input/output transistors 3, 4 and common input/output lines 5, 6 of FIG. 1 are respectively replaced by write transistors 13, 14 and data input/output lines 15, 16. The write transistors 13, 14 receive; at the gates thereof, a write column selection line (WCSL) signal. Furthermore, data read lines 17, 18 which are additionally provided are indirectly coupled to the bit lines 1, 2 via transmitting transistors 21, 22 and sensing transistors 19, 20, so that the bit line voltages are not directly coupled to the data read lines 17, 18. The sensing transistors 19, 20 and transmitting transistors 21, 22 are operating as a pre-amplifier. For more information, reference should be made to the above mentioned paper.
In the circuit of FIG. 2, since the bit line signals are pre-amplified by the sensing transistors 19, 20 and transmitting transistors 21, 22 before applied to the data read lines 17 and 18, even the weak signals from the bit lines 1, 2 can be successfully delivered into the data read lines 17 and 18. Therefore, the sensing time is not required and thus, the data access time can be reduced. However, this circuit has additional elements for realizing the fast access time, resulting in the low chip density.